GL Introduces New Generation High-Density (HD) T1/E1 Boards

Gaithersburg, Maryland, USA - April 18, 2005 - GL Communications Inc, today announced the release of a new generation of High Density (HD) T1/E1 boards.

This new generation T1/E1 HD boards can process hundreds of channels or timeslots simultaneously on T1 and E1 lines. These boards are smaller, efficient, and significantly faster as compared to PCI boards. They are fully compatible with the latest T1/E1 software that includes several new applications and enhancements (Refer to the "New Generation HD T1/E1 Boards" and "What's New In Current Version" link for complete details).

Some highlights for HD T1/E1 boards are given below:

Size (Form Factor) of the new HD boards is much smaller, its size being 4.2" x 7.1" as compared to the older boards 4.2" x 9.2".
Speed of the HD boards is significantly greater. The new boards use DMA and a 32-bit wide bus as compared to the older boards that used an interrupt driven scheme and a 16-bit wide bus.
CPU Utilization with the newer boards is negligible. One can easily put 12 new dual HD boards in one rack system running many applications on all 24 ports simultaneously. With the older boards, there was a practical limit of 4 dual boards including the limitations in overall capability as well. For example, using the new HD boards, one can simulate echo on hundreds of timeslots by invoking Delay-Attenuate Timeslots application on all 24 timeslots of each Dual T1/E1 board (up to 12 boards in a rack system) without considerably imposing the CPU utilization.

Additionally, unlike older boards, new HD Boards are compatible with Dual Processor motherboards and software that simulates dual processors (i.e. Hyper-Threading).
Improved On-Board Logic provided by upgraded FPGA can handle almost all specialized functions with a single load mechanism unlike the multiple loads on older boards. This permits special applications to be run simultaneously without T1 E1 line interference associated with unloading and loading of multiple applications. For example, FDL applications can be run simultaneously with BERT or Error Insertion applications.

Additionally, various features have now been incorporated into the FPGA hardware. Some significant enhancements introduced in these boards are listed below:

Enhancements to BERT Application

Sub-channel BERT
Non-contiguous timeslot BERT
User defined programmable patterns
Independent transmit and receive BERT sections
Inverting patterns
Bit error rate insertion

Incorporation of 'signaling bits' called CAS (Channel Associated Signaling) at the hardware level.
A new application, Single Channel Low Echo Path Delays has been introduced to take advantage of the FPGA hardware. This implementation shortens the internal delay to as low as about 1 ms.
Another special application is included that allows handling of 'A-law all bits inverted' on T1 lines. In general any code conversion such as bit-inversion can be performed in the FPGA of the high-density boards.

Currently HD boards are only available in Dual T1 and Dual E1 port versions with compatible T1/E1 Analyzer Software. Kindly refer to the "New Generation HD T1/E1 Boards" link for further details.

About GL Communications Inc

Founded in 1986, GL Communications Inc. is a leading supplier of rigorous, PC and Laptop-based test, analysis, and simulation equipment to the telecommunications industry. The company offers a wide range of products and services designed to aid telecommunications engineers working in research and development as well as those responsible for operations and ongoing quality assurance. For information on GL's test, analysis and simulation products visit www.gl.com

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