Newsletter: GL Introduces New Generation High-Density (HD) T1/E1 Boards
Welcome to the April issue of GL Communications' Newsletter. This month GL officially released a new generation of T1 and E1 boards called the High-Density (HD) Boards.
These High-Density (HD) boards can process hundreds of channels or timeslots simultaneously on T1 and E1 lines. The boards are smaller, more CPU efficient, and significantly faster than the older PCI boards. They are fully compatible with the latest T1/E1 Software Version 4.86, which includes virtually all previous applications and several new applications and enhancements.
NOTE! For a limited time, older boards can be upgraded to the new HD Versions at a substantial discount.
Highlights on the advantages of HD boards:
- Size of the new HD boards is much smaller, its size being 4.2" x 7.1" as compared to the older boards 4.2" x 9.2". This allows the boards to easily fit inside PCs with smaller form factors
- Faster processing with a 32-bit wide bus and DMA technology that prevents conflicts with existing devices as compared to the older boards that used a 16-bit wide bus and interrupt driven mechanism
- Negligible CPU utilization that permits users to easily install at least as many as 12 HD dual boards in one rack system running many applications on all T1 or E1 ports and timeslots simultaneously
- Compatible with motherboards that incorporate Hyperthreading and Dual Processor architectures
- Improved On-Board logic (upgraded FPGA) can handle almost all specialized functions with a single load mechanism, unlike the older boards. This gives the user the ability to run many special applications simultaneously and without 'T1/E1 line interference' associated with unloading and loading of multiple applications
New features incorporated into FPGA hardware:
- CAS (Channel Associated Signaling) signaling bits are efficiently processed in FPGA
- Single Channel Low Echo Path Delay application to shorten the internal echo delay to as low as about 1 ms
- Provision for A-law-All bits inverted code conversion. In general, any code conversion such as bit-inversion can be performed in the FPGA of the HD boards
- Significant enhancements in BERT application have been incorporated into FPGA hardware. These include sub-channel, non-contiguous timeslot, user-defined programmable patterns, independent transmit and receive BERT sections, inverting patterns and bit-error rate insertion
Currently HD boards are only available in Dual T1 and Dual E1 port versions with compatible T1/E1 Analyzer Software. Please refer to the new generation HD T1/E1 Boards for further details.
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